This invention relates generally to improved means and methods for testing the operation of digital circuits such as are employed in digital data processing systems.
As the use of data processing systems continues to increase, it is becoming of increasing importance to provide improved means and methods for testing and diagnosing failures in the various components and circuits of these systems.
A basic known approach for the testing of digital circuits invovles synchronously stimulating a unit to be tested and a standard unit with a desired signal input, and then synchronously comparing the resultant output signal from these units for equality at appropriate times relative to the system clock so as to determine whether the unit being tested is operating properly. Typically, in such synchronous comparison testers, the test signal input must be provided with sufficient setup and hold times relative to clock time, and comparison times must be chosen so as to permit sufficient time for the output signals from the units to have stabilized prior to the occurrence of the clock taking into account the longest permissible propagation delay. One typical known way of meeting these requirements without adding undue complexity is to slow the clock rate, but this has the disadvantage of masking failures which only occur at normal (faster) opeating speeds.
The above described synchronous comparison approach also has the disadvantage of failing to detect certain other types of errors which could also be troublesome during normal system operation. For example, glitches or noise occurring in the output signal of the unit under test at times outside of the comparison time periods would go undetected during testing, and yet could be of significance during normal system operation.